這是太重要的發展！這CuLitho軟體庫與搭配的Nvidia GPU叢集，能達成晶片製造上運算式微影(Computational Lithography)計算速度一個數量級（十倍以上）的提升，內文是說已達到42倍的計算速度提升（而且還尚未使用AI仿真計算技術），同時，所需的處理器數量由4萬顆CPU降為2千顆GPU，耗電量大幅降低，而且製造精度、良率與產能也得到同等的提升！
在晶片上的導線線徑已經比曝光機所用光的波長短時（例如深紫外光(DUV)準分子雷射光源，如氟化氪(KrF)產生的248 nm波長和氟化氬(ArF)的193 nm波長，可用來製造14nm以上的晶片，而極紫外光微影技術（EUV）使用的是13.5 nm波長的光，但要製造7 nm以下線距的晶片），這時光罩上的開孔所形成的圖像(Pattern），就必須以電腦進行設計，透過光的干涉與繞射，正確聚焦於晶圓，以讓光阻劑與其反應，如底片曝光一樣形成所需的圖像，然後進行後續的蝕刻作業，才能形成所需的圖像（導線與半導體元件的組合）。（參https://www.iner.gov.tw/eip/msn.aspx?datatype=YW5hbHlzaXM=&id=MjAz）
因此，每一個光罩的設計（例如Nvidia H100就用到89層光罩），並不可能人工作業（中國的手刻晶片大師都哭暈了！），都要透過極度複雜的演算法，經過多台伺服器（以前台積電使用了共4萬顆CPU的伺服器叢集，有望可以降為500台共2千顆Nvidia H100GPU的伺服器）與多日計算（以前是兩週，現在可降為8小時）才能得到。
這個半導體製造速度與耗電/良率/產能的進步是歷史性的成就！恭喜Nvidia（難怪其股價噴出），與採用這CuLitho軟體庫的TSMC及ASML。
Nvidia Brings GPU Acceleration to Computational Lithography
「Nvidia has built a software library for the acceleration of computational lithography workloads, enabling order-of-magnitude speedups for these workloads when combined with the latest GPU hardware. The library, CuLitho, will be used at Taiwan Semiconductor Manufacturing Co. (TSMC) beginning in June. Accelerating computational lithography has the potential to improve yield, thereby reducing cost per chip. Other benefits include reducing the carbon footprint associated with this workload, faster turnaround and enabling advanced process nodes with tiny feature sizes.
“CuLitho will accelerate not just mask making but the entire development cycle type for any foundry that uses it,” said Vivek Singh, VP of accelerated computing at Nvidia. “The second benefit of CuLitho is even more profound… the current calculations of computational lithography, large as they are, may not actually be good enough to make the chips of tomorrow. Those chips will require new technologies, which could require 10 times more computation.”
Computational lithography as a field began around 30 years ago when feature sizes reduced below the wavelength of light used for patterning. Masks had to be adjusted to compensate for diffraction patterns, which began to affect the features created. As feature sizes have shrunk further, algorithms that calculate holes in the mask required to produce coherent features in silicon have become more and more complex, and the shapes they predict are less and less intuitive. Calculating the exact sizes and shapes of the holes in the mask has become a significant computational problem. It is the largest computational workload in chip design and manufacturing today, consuming tens of billions of CPU hours annually.」
